A process for fabricating a MOS-based device by way of trench formation may be achieved in the manner as illustrated in FIGS. 1-3. As shown in FIG. 1, a thin oxide layer 30 is formed on a lightly doped N-type epitaxial layer 20. P-type impurities are then implanted into the epitaxial layer 20 at respective dose and implant energy levels to form a blanket implant region 40b and selective higher doped implant regions 40a.
As shown in FIG. 2, implanted dopants in regions 40b and 40a are then diffused to form a P-type body region 40. N-type impurities are then implanted into the P-type body region 40, followed by diffusion, to obtain heavily doped N-type source regions 50.
As shown in FIG. 3, trenches 100 are formed by a RIE (Reactive Ion Etching) step and a sacrificial oxide layer is formed to remove damage generated by the RIE. Following the sacrificial oxide layer removal, polysilicon gate electrodes 70 are formed via the steps of gate.
Such a prior art process may be problematic in that the step of forming the sacrificial oxide layer should be performed at high temperature in order to remove the damaged layer caused by the RIE and round the top and bottom edges of the trench. In this respect, the doping profiles of the P-type body region 40 and N-type source regions 50 are modified by the high temperature thermal treatment. A short channel as well as an unwanted gate threshold voltage may result since the heavily doped N-type impurities are diffused and the concentration of P-type dopants decreases in the channel region. Leakage currents may also increase between drain and source regions. In addition, for MOS devices, an appropriate insulating voltage may be hard to attain because the gate oxide layer 60 has a thickness in the 400 to 500 .ANG. range and the concentration of P-type dopants is low in the channel region. Thus, notwithstanding this conventional method of forming MOS-based switching devices having trench gates, there continues to be a need for improved methods which limit the above-described problems.